1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly to a structure of an input protection transistor in a semiconductor device including a memory transistor having a double-layered gate. The invention further relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
FIG. 1 is a plan view of a semiconductor device to be a background of the present invention. Referring to FIG. 1, a semiconductor device 2 comprises a RAM (Random Access Memory) region 4, an EPROM (Erasable Programmable Read Only Memory) region 6, a CPU (Central Processing Unit) region 8, and a peripheral circuit 10 having input/output functions, provided at peripheries of the above regions 4, 6 and 8. FIGS. 2A-2C show the structure of an input protection circuit in a region II including the peripheral circuit shown in FIG. 1.
The structure of the input protection circuit will now be described with reference to FIGS. 1 and 2A-2C. An electrode pad 12 for receiving an electrical signal to be supplied to the semiconductor device 2 is provided at peripheral portions of the semiconductor device 2. The electrode pad 12 is connected through an interconnection 14 to an inverter 16 as one example of an internal logic circuit. Although the internal logic circuit is not limited to the inverter, the inverter will be described as one example of a CMOS (Complementary Metal Oxide Semiconductor) device. Such internal logic circuits are provided in the peripheral circuit 10, the CPU 8, the EPROM 6 and the RAM 4. That is, a large number of internal logic circuits are provided in the semiconductor device 2. As shown in FIG. 2B, the inverter 16 comprises a P channel MOS transistor 15 and an N channel MOS transistor 17.
An input protection transistor 18 is connected to the interconnection 14 for electrically connecting the inverter 16 and the electrode pad 12 so as not to apply an overvoltage to the inverter 16. Referring to FIG. 2C, the input protection transistor 18 comprises: N.sup.+ source/drain regions 22, 24 formed apart from each other in a major surface of a P type semiconductor substrate 20; N.sup.- source/drain regions 23, 25 formed adjacently to the N.sup.+ source/drain regions 22, 24, respectively; a gate insulator film 26 formed on a surface region of the semiconductor substrate 20 between the N.sup.- source/drain regions 23 and 25; and a gate electrode 28 formed on the gate insulator film 26. The input protection transistor 18 is an N channel transistor. In the input protection transistor 18, one N.sup.+ source/drain region 22 is connected to the interconnection 14, while the other N.sup.+ source/drain region 24, the gate electrode 28 and the semiconductor substrate 20 are all grounded. The gate electrode 28 is grounded in order that the transistor 18 is always OFF.
When a human body touches the electrode pad 12, a high voltage caused by friction between the human body and clothes is applied to the electrode pad 12. At this time, a charge flows into the semiconductor substrate 20 through the interconnection 14 and through the N.sup.+ source/drain region 22, so that the charge is prevented from flowing into a gate electrode of the inverter 16. Therefore, even when a surge voltage is applied to the electrode pad 12, the inverter 16 is hardly destroyed. It is considered that the charge flows into the semiconductor substrate 20 rather than into the gate electrode of the inverter 16 because the semiconductor substrate 20 has a larger capacitance than the gate electrode of the inverter 16.
FIGS. 3A-3Q are cross sectional views showing a process for manufacturing the semiconductor device to be the background of the invention.
Referring to FIG. 3A, a P type silicon substrate 20 comprises an EPROM region 32, a CMOS region 34 and an input protection transistor region 36. These regions are drawn as adjacent to one another in the figure; however, it should be understood that the regions are not necessarily adjacent to one another, but exist on one substrate. In order to simplify the description, the structure of only one memory device in the EPROM region 32, of one CMOS device in the CMOS region 34 and of one transistor in the input protection transistor region 36 is shown, and the detailed structures of the RAM 4, the EPROM 6, the CPU 8 and peripheral circuit 10 shown in FIG. 1 are not shown in the figures.
The EPROM region 32 is a region where the EPROM 6 is to be formed. The CMOS region 34 is a region where the inverter 16 is to be formed, and comprises a P channel transistor region 33 and an N channel transistor region 35. The input protection transistor 36 is a region where the input protection transistor 18 is to be formed. A silicon oxide film 38 is formed on a major surface of the P type silicon substrate 20 by thermal oxidation. A resist film 40 is formed in only the P channel transistor region 33 by employing photolithography, and boron is ion-implanted into the major surface of the silicon substrate 20, with the resist film 40 used as a mask. Thus, a boron ion-implanted layer 42 is formed in the surfaces of the EPROM region 32, N channel transistor region 35 and input protection transistor region 36. The resist film 40 is then removed.
Referring to FIG. 3B, a resist film 44 is formed by photolithography on the EPROM region 32, N channel transistor region 35 and input protection transistor region 36. With the resist film 44 used as a mask, phosphorus is ion-implanted into the surface of the silicon substrate 20 so as to form a phosphorus ion-implanted layer 46 in the surface of the P channel transistor region 33. The resist film 44 is thereafter removed.
Referring to FIG. 3C, annealing is performed so as to form a P well 48 and an N well 50 in a surface region of the P type substrate 20. The oxide film 38 is then removed.
Referring to FIG. 3D, a silicon oxide film 39 is formed on the whole surface of the semiconductor substrate 20, and a silicon nitride film 52 is formed on the silicon oxide film 39, thereby to form a resist film on the silicon nitride film 52. This resist film is patterned so as to cover an element forming region. The silicon nitride film is etched, with a resultant resist film 54 thus formed employed as a mask, thereby leaving the silicon nitride film 52 only at the element forming region.
As shown in FIG. 3E, all of the P channel transistor region 33 in the CMOS region 34 is covered with a resist film 56. Boron is then ion-implanted into a surface region of the P well 48, with the resist films 54 and 56 employed as masks, so that a boron ion-implanted layer 58 is formed. The resist films 54 and 56 are thereafter removed. Regions uncovered with the silicon nitride film 52 are oxidized by a LOCOS (Local Oxidation of Si) method, thereby to form a field oxide film 60 as shown in FIG. 3F. A thickness of the field oxide film 60 is approximately 6000 .ANG.. Then, the nitride etched away. Next, a gate oxide film 66 having a thickness of 370 .ANG. is newly formed on the surface of the silicon substrate 20.
Referring to FIG. 3G, a polysilicon film is formed on the overall surface of the silicon substrate 20 and then doped with phosphorus, thereby to be made of N type. A resist film 64 is then formed on the polysilicon film in the EPROM region 32 by photolithography. Thereafter, with the resist film 64 used as a mask, the polysilicon film is etched, thereby leaving the polysilicon film 62 in only the EPROM region 32. The resist film 64 is then removed. The polysilicon film 62 is to be a floating gate of EPROM and is approximately 3000 .ANG. thick. Next, in order to control a threshold voltage of a MOS transistor repetition of applying the resist and implanting ions carries out channel doping for each transistor, and then the oxide film 66 other than beneath the polysilicon film 62 is then removed.
With reference to FIG. 3H, a gate oxide film 26 is formed in the CMOS region 34 and the input protection transistor region 36 by oxidation. An oxide film 68 is formed at the side surface and the upper surface of the polysilicon film 62 at this time. Thereafter, a polysilicon film 70 is formed on the overall surface of the silicon substrate 20 and then doped with phosphorus. A molybdenum silicide film 72 is formed on the polysilicon film 70. The polysilicon film 70 is approximately 2800 .ANG. in thickness, while the molybdenum silicide film 72 is approximately 2300 .ANG. in thickness. The oxide film 26 is approximately 250 .ANG. in thickness in the input protection transistor region 36.
Referring to FIG. 3I, a resist film 76 is formed on the overall surfaces of the CMOS region 34 and input protection transistor region 36 and in a gate forming region of the EPROM region 32. Etching is carried out with the resist film 76 used as a mask, and the molybdenum silicide film 72, the polysilicon film 70, the oxide film 68, the polysilicon film 62 and the gate oxide film 66 are all removed in regions of the EPROM region 32 other than its gate forming region. The remaining polysilicon film 62 constitutes a floating gate 78, while the remaining polysilicon film 70 and molybdenum silicide film 72 together constitute a control gate 80. The resist film 76 is then removed.
With reference to FIG. 3J, with the control gate 80 and molybdenum silicide film 72 employed as masks, arsenic is ion-implanted into the overall surface of the semiconductor substrate 20, thereby to form an N.sup.+ source/drain region 82 in the surface region of the P well 48. A gate length La of the floating gate 78 and that of the control gate 80 are both approximately 1.2 .mu.m.
With reference to FIG. 3K, a resist film 84 is formed on the gate forming region of each of the CMOS region 34 and input protection transistor region 36 and on the overall surface of the EPROM region 32. Etching is then carried out with the resist film 84 used as a mask, thereby removing the molybdenum silicide film 72 and polysilicon film 70 in the regions of the CMOS region 34 and input protection transistor region 36 other than their gate forming regions. Thus, gate electrodes 86 and 88 in the CMOS region 34 and a gate electrode 28 in the input protection transistor region 36 are formed. The resist film 84 is thereafter removed.
As shown in FIG. 3L, a resist film 92 is formed on the overall surfaces of the EPROM region 32 and the P channel transistor region 33 which is a portion of the CMOS region 34. Phosphorus is ion-implanted with the resist film 92, and the gate electrodes 88 and 28 used as masks, thereby forming an N.sup.- source/drain region 94 in the N channel transistor region 35 and N.sup.- source/drain regions 23 and 25 in the input protection transistor region 36. The N.sup.- source/drain regions 23, 25 and 94 are regions having low concentration impurities. The resist film 92 is then removed.
A gate length Lb of the gate electrode 88 in the N channel transistor region 35 is approximately 1.3 .mu.m, while that Lc of the gate electrode 86 in the P channel transistor region 33 is approximately 1.5 .mu.m.
Referring to FIG. 3M, an insulator film is formed on the overall surface of the silicon substrate 20 having gate electrodes on its surface, and the insulator film is then subjected to anisotropical etching. Sidewalls 98 are thus formed at the peripheries of the gates 78, 80, 86, 88 and 28. Thereafter, a resist film 106 is formed on the overall surface of the P channel transistor region 33. Arsenic is ion-implanted, with the resist film 106, the gates 28, 78, 80 and 88, and their surrounding sidewalls 98 employed as masks. Accordingly, an N.sup.+ source/drain region 108 in the N channel transistor region 35 and N.sup.+ source/drain regions 22 and 24 in the input protection transistor region 36 are formed, resulting in a so-called LDD (Lightly Doped Drain) structure. At this time, an impurity concentration of the N.sup.+ source/drain region 82 in the EPROM region 32 becomes further increased. The resist film 106 is then removed.
Referring to FIG. 3N, a resist film 112 is formed over the overall surface of the EPROM region 32 and over that of the N channel transistor region 35 and input protection transistor region 36. Thereafter, boron is ion-implanted, with a resist film 112, a gate electrode 86 and its surrounding sidewalls 98 used as masks. A P.sup.+ source/drain region 114 is thus formed in the P channel transistor region 33. The resist film 112 is then removed.
With reference to FIG. 30, over the whole surface of the silicon substrate 20 is formed a BPSG (Boro-Phospho Silicate Glass) film 116. A thickness of the BPSG film 116 is approximately 10000.ANG.. A resist film 118 is then formed on a predetermined region of the BPSG film 116. Etching is then carried out with the resist film 118 used as a mask so as to form a contact hole 120. The resist film 118 is thereafter removed.
As shown in FIG. 3P, an Al--Si film 122 is formed on the BPSG film 116 so as to fill the contact hole 120. A resist film 124 is then formed in a predetermined region on the Al--Si film 122 and is then subjected to etching, with the resist film 124 used as a mask, thereby forming an Al--Si interconnection layer 122. A thickness of the Al--Si interconnection layer 122 is approximately 8500.ANG.. The resist film 124 is thereafter removed.
Referring to FIG. 3Q, over the whole surface of the silicon substrate 20 is formed a protection film 126 made of a silicon nitride or a silicon oxide. Through all the foregoing processing steps, there are formed a memory transistor 128 in the EPROM region 32, internal logic transistors 15 and 17 in the CMOS region 34, and an input protection transistor 18 in the input protection transistor region 36.
Next, an operation of a memory cell in the EPROM region will now be described with reference to FIG. 4. When information is written into a cell, a high voltage (10-20V) is applied to a control gate 80 and a drain 82b of a memory cell 128, so that avalanche carrier (electrons) is produced at end portions of the drain 82b. The application of a positive voltage to the control gate 80 causes the electrons to be injected into a floating gate 78, overcoming an energy barrier of a gate insulator film 66. Since the floating gate 78 is not electrically connected to the other circuit portions, the gate is capable of storing a charge semipermanently. When the charge is stored into the floating gate 78, a threshold voltage Vth of the memory cell becomes higher than that before the injection of electrons. States before and after injecting electrons into the floating gate 78 are made correspondent to "1" and "0" (e.g., "1" represents the state that Vth is high, while "0" represents the state that Vth is low), thus causing the memory cell 128 to have a memory function. When the electrons stored in the floating gate 78 are discharged from the memory cell, ultraviolet rays are directed to the cell 128.
The LDD structure is intended to be formed in the drain of the N channel transistor 17 in the CMOS region 34, in the above described product, for the purpose of preventing a change in the threshold voltage due to hot carrier, caused along with reduction of a channel length and also increasing a breakdown voltage between the source/drain.
In the semiconductor device manufactured through the above manufacturing steps, all the N channel transistors, i.e., the input protection transistor 134 and the internal logic transistor 132 other than those in the EPROM region 32 have the LDD structure. Therefore, the following problems are involved.
Referring to FIG. 2C, since the N.sup.- source/drain 23, 25 in the input protection transistor 18 has a higher resistance value than that of the N.sup.+ source/drain 22, 24, an application of a surge voltage to the electrode pad 12 generates heat at the N.sup.- source/drain, thereby sometimes destroying the N.sup.- source/drain.
In addition, the input protection circuit shown in FIGS. 2A and 2C is connected also to an interconnection for supplying an information writing voltage to the memory cell in the EPROM region 32 in order to protect the memory cell. However, the input protection transistor is sometimes destroyed due to an occurrence of an overshoot voltage and thus a generation of heat in the N.sup.- source/drain, similarly to the above case, when a voltage for writing is applied.